1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly relates to a semiconductor device including an FBC (Floating Body Cell) which stores information by accumulating majority carriers in a body in a floating state in a field effect transistor (FET).
2. Background Art
The fabrication of a related DRAM cell having one transistor and one capacitor which includes a trench capacitor or a stacked capacitor is getting difficult with its miniaturization. However, as an alternative memory cell thereto, a new memory cell FBC which stores information by accumulating majority carriers in a body in a floating state in an FET (Field Effect Transistor) formed on a Silicon on Insulator (SOI) or the like (See Document 1: Japanese Patent Application Laid-open No. 2003-68877, and Document 2: Japanese Patent Application Laid-open No. 2002-246571, for example) was proposed.
An element unit of this memory cell to store one bit of information has only one MISFET (Metal Insulator Semiconductor Field Effect Transistor), whereby the area occupied by one bit is small, so that a mass storage element can be formed on a limited silicon area. Accordingly, it is thought that this can contribute to an increase in storage capacity.
The reading of data from such a MISFET is performed by current read (See Document 3: 2002 IEEE International Solid-State Circuits Conference, “Memory Design Using One-Transistor Gain Cell on SOI”, p152, p153, p454). Namely, a word line connected to a gate of the MISFET is set, for example, to 1.5 V, a bit line connected to a drain is set, for example, to as low as 0.2 V, the transistor is operated in a linear region, and “1” data and “0” data are distinguished by detecting current difference using an effect (body effect) in which a threshold voltage Vth of the transistor differs according to the number of holes accumulated in the body. Incidentally, the reason the voltage of the bit line is set to as low as 0.2 V in a read operation in this example is that if the voltage of the bit line is set high and biased to a saturation state, there is a possibility that when the “0” data is read, the “0” data cannot be correctly detected because the data is changed into the “1” data by impact ionization.
In a related semiconductor memory device using FBCs, one sense amplifier is provided for plural bit lines, and when the sense amplifier is connected to a bit line, one bit line is selected from the plural bit lines and connected. This makes it possible to realize a reduction in the number of sense amplifiers and a reduction in chip area. The reason which makes this configuration possible is based on the premise that the FBC is capable of non-destructive read-out. In other words, this is because the FBC is thought to have a characteristic that data in a memory cell from which the data is not read is not destroyed even when a word line rises, and if the word line returns to a holding level, the data remains held as it was before.
However, in the later FBC characteristic evaluation, it has turned out that the FBC is not completely a non-destructive read-out cell. This is because it has proved that a charge pumping phenomenon exerts an influence on the characteristic of the memory cell. This charge pumping phenomenon is a phenomenon in which holes gradually disappear at an interface between a silicon surface and a gate insulating film (for example, SiO2) when operations of bringing the silicon surface into an inversion state and an accumulation state are alternately repeated by pumping the gate of the transistor a plurality of times.
The number of holes which disappear by one change of state of inversion/accumulation depends on an interface state density Nit of the Si—SiO2 interface. If Nit=1×1010 cm−2 is assumed, the area of the Si—SiO2 interface is 1.0×10−10 cm2 per cell when the cell transistor has W/L=0.1 μm/0.1 μm, whereby the number of holes which disappear by one change of state is approximately one on average per cell. The difference in the number of holes between “1” data and “0” data in one FBC is approximately 1000. This means that after approximately 1000-time pumping of the word line, the “1” data completely changes to the “0” data. Actually, the read margin of the “1” data disappears after approximately 500-time pumping, and the risk of causing failures increases. Accordingly, it turns out that the FBC is neither a destructive read-out cell nor a complete non-destructive read-out cell. It turns out that it is, so to speak, a quasi non-destructive read-out cell.
If a sense amplifier of a related system is used in the aforementioned case, since data is not written back even if a word line rises, a failure in which the “1” data has changed to the “0” data is caused if the word line rises approximately 500 times before a refresh operation is performed. Therefore, apart from whether the memory cell is selected for read/write, the design of a sense amplifier which takes some measures against the charge pumping phenomenon is needed for all of the memory cells holding the “1” data whose word lines are activated.
Moreover, there is a problem that the related system sense amplifier is inefficient in the refresh operation. Namely, there is a problem that the number of memory cells which can be refreshed in one refresh cycle is smaller as compared with the conventional DRAM. For example, in a sense amplifier disclosed in Document 3, the refresh efficiency reduces to ⅛. Accordingly, when the refresh time is the same, it is necessary to set the refresh cycle eight times as frequently as the conventional DRAM, and correspondingly the proportion in which the normal operation cannot be performed increases.
Furthermore, in the configuration of the semiconductor memory device in Document 3, there is a problem that the number of memory cells which can be accessed in a high-speed column access is limited. In other words, when a mode in which data in memory cells are read by raising a word line, latched in a sense amplifier, and continuously accessed at high speed by switching the column address to thereby increase data transfer rate (this mode is also called the Fast Page Mode) is used, the number of accessible data reduces to ⅛ as compared with the normal DRAM.
On the other hand, when sense amplifiers are provided independently corresponding to respective bit lines, the cell current flows from each sense amplifier to a source of a memory cell in a write operation, which causes a problem that current consumption increases. Namely, in a write cycle, a connection between each sense amplifier and each bit line is opened irrespective of whether each memory cell is a memory cell into which data is actually written, and therefore the cell current flows from each sense amplifier to each memory cell. Besides, the cell current continues flowing until one write cycle is completed.